Bachelor/ Master Thesis - Implementation of a Latch-Based Register File for RISC-V Cores

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• Build your technical foundation: Get familiar with Infineon’s code generation framework, RISC-V processor architectures, and register-file implementations
• Develop latch-based register-file solutions: Investigate latch-based storage architectures and clocking schemes for processor register files, then develop and implement a configurable latch-based register-file solution
• Evaluate implementation options: Assess different implementation options with respect to timing, area, power, and robustness
• Analyze design-for-testability: Analyze DFT aspects and compare latch-based and flip-flop based approaches
• Integrate your work: Integrate the solution into the code-generation framework and generate implementations for various RISC-V cores
• Verify and validate: Perform functional verification, synthesis, and implementation studies
• Contribute to research: Contribution to a publication is desired

• Education: Bachelor's or master's student in Computer Science, Electrical Engineering, or similar
• Interests: Bring a background in design, synthesis, timing analysis, and simulation of digital circuits using (System-)Verilog or VHDL
• Knowledge: Have an understanding of digital design concepts such as latches, flip-flops, clock gating, and DFT
• Skills: Proficiency in Python, Linux, and Git; programming skills are a must
• Experience: Ideally, have experience with processor microarchitecture and RISC-V
• Availability: You are available for an upfront internship to get familiar with some of techniques before the thesis starts
• Language skills: Fluent English skills, both written and spoken; German is a plus
• CV in English
• Certificate of enrollment at university
• Excerpt of the study regulations for the thesis (if applicable)
• Latest grades transcript (not older than 6 months)
• High school report