Internship in FPGA Development

Internship at ZEISS Medical Technology in Jena. You combine studies and practice and actively work on exciting projects.

• Design and implementation of code generators for automatic generation of VHDL modules in Python
• Integration of the generated modules into an existing VHDL design
• Equivalence testing using the QuestaSim simulation environment
• Verification using the QuestaSim simulation environment
• Synthesis of the VHDL code for a representative FPGA platform
• Documentation of the work results

• Studies in engineering, ideally computer science or a comparable field
• Programming skills in Python, VHDL
• Methodical and structured way of working and analytical thinking
• Good organizational and communication skills
• Good German and English skills